BIOS-POST CODE INFO

cvl · 發(fā)表于 2006-11-21 14:20:29

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EISA POST Codes are typically output to port address 30h
ISA POST Codes are typically putput to port address 80h
AWARD Test Sequence up to Version 4.2:
<DIV align=left>
<TABLE cellSpacing=0 cellPadding=0 width="99%" align=center border=1>
<TBODY>
<TR>
<TD width="32%">CPU</TD>
<TD width="68%">BIOS sets, verifies and resets the error flags in the CPU.  Failure here is normally due to the CPU or system clock</TD></TR>
<TR>
<TD width="32%">POST Determination</TD>
<TD width="68%">BIOS determines whether the motherboard is set for normal operation or a continuous loop of POST.  If the POST test is cycled 1-5 times over and over either the jumper for this function is set to burn=in or the circuitry involved has failed</TD></TR>
<TR>
<TD width="32%">Keyboard Controller</TD>
<TD width="68%">BIOS tests the internal operations of the keyboard controller chip (8042).   Failure here is normally due to the keyboard chip</TD></TR>
<TR>
<TD width="32%">Burn In Status</TD>
<TD width="68%">1-5 will repeat if the motherboard is set to burn in.  If you haven't set the motherboard for burn-in mode, there is a short in the circuitry</TD></TR>
<TR>
<TD width="32%">Initialize Chipset</TD>
<TD width="68%">BIOS clears all DMA registers and CMOS status bytes 0E and 0F.  BIOS then initializes 8254 timer,  Failure of this test is probably due to the timer chip</TD></TR>
<TR>
<TD width="32%">CPU</TD>
<TD width="68%">A bit-pattern is used to verify the functioning of the CPU registers.  Failure here is normally down to the CPU or clock chip</TD></TR>
<TR>
<TD width="32%">RTC</TD>
<TD width="68%">BIOS verifies that the real time clock is updating CMOS at normal intervals.  Failure is normally the CMOS/RTC or the battery</TD></TR>
<TR>
<TD width="32%">ROM BIOS Checksum</TD>
<TD width="68%">BIOS performs a checksum of itself against a predetermined value that will equal 00.  Failure is down to the ROM BIOS</TD></TR>
<TR>
<TD width="32%">Initialize Video</TD>
<TD width="68%">BIOS tests and initializes the video controller.  Failure is normally the video controller (6845) or an improper setting of the motherboard or CMOS</TD></TR>
<TR>
<TD width="32%">PIT</TD>
<TD width="68%">BIOS tests the functionality of channels 0, 1, and 2 in sequence.  Failure is normally the PIT chip (8254/53)</TD></TR>
<TR>
<TD width="32%">CMOS Status</TD>
<TD width="68%">Walking bit pattern tests CMOS shutdown status byte 0F.  Failure normally in CMOS</TD></TR>
<TR>
<TD width="32%">Extended CMOS</TD>
<TD width="68%">BIOS checks for any extended information of the chipset and stores it in the extended RAM area.  Failure is normally due to invalid information and can be corrected by setting CMOS defaults.  Further failure indicates either the chipset or the CMOS RAM</TD></TR>
<TR>
<TD width="32%">DMA</TD>
<TD width="68%">Channels 0 and 1 are tested together with the page registers of the DMA controller chip (8237).  Failure is normally due to the DMA chips</TD></TR>
<TR>
<TD width="32%">Keyboard</TD>
<TD width="68%">The 8042 keyboard controller is tested for functionality and for proper interfacing functions.  Failure is normally due to the 8042 chip</TD></TR>
<TR>
<TD width="32%">Refresh</TD>
<TD width="68%">Memory refresh is tested; the standard with walking - bit patterns.  Failure is normally the PIT chip in AT's or the DMA chip in AT's</TD></TR>
<TR>
<TD width="32%">Memory</TD>
<TD width="68%">The first 64K of memory is tested with walking bit patterns.  Failure is normally due to the first bank of ram or a data line</TD></TR>
<TR>
<TD width="32%">Interrupt Vectors</TD>
<TD width="68%">The BIOS interrupt vectors table is loaded to the first bank of RAM.  Failure here is not likely since memory in the area has been tested.  If failure does occur suspect the BIOS or RTC</TD></TR>
<TR>
<TD width="32%">Video ROM</TD>
<TD width="68%">Video ROM is initialized which performs an internal diagnostic before returning control to the system BIOS.  Failure is normally the video adapter or the BIOS</TD></TR>
<TR>
<TD width="32%">Video Memory</TD>
<TD width="68%">This is tested with a bit pattern.   This is bypassed if there is a ROM on the video adapter.  Failure is normally down to the memory on the adapter</TD></TR>
<TR>
<TD width="32%">PIC</TD>
<TD width="68%">The functionality of the interrupt controller chip(s) is tested (8259).  Failure is normally due to the 8259 chips but may be the clock</TD></TR>
<TR>
<TD width="32%">CMOS Battery</TD>
<TD width="68%">BIOS verifies that CMOS byte 0D is set which indicates the CMOS battery power.  Suspect the battery first and the CMOS second</TD></TR>
<TR>
<TD width="32%">CMOS Checksum</TD>
<TD width="68%">A checksum is performed on the CMOS.   Failure is either incorrect setup, the CMOS chip or battery.  If the test is passed, the information is used to configure the system</TD></TR>
<TR>
<TD width="32%">Determine System Memory</TD>
<TD width="68%">Memory up to 640K is addressed in 64K blocks.  Failure is normally due to an address line or DMA chip.  If all the memory is not found there is a bad RAM chip or address line in the 64K block above the amount found</TD></TR>
<TR>
<TD width="32%">Memory Test</TD>
<TD width="68%">Tests are performed on any memory found and there will normally be a message with the hex address of any failing bit displayed at the end of boot</TD></TR>
<TR>
<TD width="32%">PIC</TD>
<TD width="68%">Further testing is done on the 8259 chips</TD></TR>
<TR>
<TD width="32%">CPU Protected Mode</TD>
<TD width="68%">The processor is placed in protected mode and back into real mode; the 8042 is used for this.  In case of failure suspect the 8042, CPU, CMOS, or the BIOS in that order</TD></TR>
<TR>
<TD width="32%">Determine Extended Memory</TD>
<TD width="68%">Memory above 1MB is addressed in 64K blocks.  The entire block will be inactive if there is a bad RAM chip on a block</TD></TR>
<TR>
<TD width="32%">Test Extended Memory</TD>
<TD width="68%">Extended memory is tested with a series of patterns.  Failure is normally down to a RAM chip, and the hex address of the failed bit should be displayed</TD></TR>
<TR>
<TD width="32%">Unexpected Exceptions</TD>
<TD width="68%">BIOS checks for unexpected exceptions in protected mode.  Failure is likely to be a TSR or intermittent RAM failure</TD></TR>
<TR>
<TD width="32%">Shadow Cache</TD>
<TD width="68%">Shadow RAM and cache are activated.   Failure may be due to the cache controller or chips.  Check the CMOS first for invalid information</TD></TR>
<TR>
<TD width="32%">8242 Detection</TD>
<TD width="68%">BIOS checks for an Intel 8242 keyboard controller and initializes it if found.  Failure may be due to an improper jumper setting or the 8242</TD></TR>
<TR>
<TD width="32%">Initialize Keyboard</TD>
<TD width="68%">Failure could be the keyboard or controller</TD></TR>
<TR>
<TD width="32%">Initialize floppy</TD>
<TD width="68%">All those set in the CMOS.  Failure could be incorrect CMOS setup or floppy controller or the drive</TD></TR>
<TR>
<TD width="32%">Detect Serial Ports</TD>
<TD width="68%">BIOS searches for and initializes up to four serial ports at 3F8, 2F8, 3E8, and 2E8.  Detection failure is normally due to an incorrect jumper setting somewhere or an adapter failure</TD></TR>
<TR>
<TD width="32%">Detect Parallel Ports</TD>
<TD width="68%">BIOS searches for and initializes up to four parallel ports at 378, 278, 3BC, and 2BC.  Detection failure is normally due to an incorrect jumper setting somewhere or an adapter failure</TD></TR>
<TR>
<TD width="32%">Initialize Hard Drive</TD>
<TD width="68%">BIOS initializes any hard drive(s) set in the CMOS.  Failure could be due to invalid CMOS setup, hard drive or controller failure</TD></TR>
<TR>
<TD width="32%">Detect NPU Coprocessor</TD>
<TD width="68%">Initialization of any NPU coprocessor found.  failure is due either to invalid CMOS setup or the NPU is failing</TD></TR>
<TR>
<TD width="32%">Initialize Adapter ROM</TD>
<TD width="68%">Any Adapter ROM's between C800 and EFFF are initialized.  The ROM will do an internal test before giving back control to the system ROM.  Failure is normally due to the adapter ROM or the attached hardware</TD></TR>
<TR>
<TD width="32%">Initialize External Cache</TD>
<TD width="68%">Any external cache to the 486 is enabled.  Failure would indicates invalid CMOS setup, cache controller or chip failure</TD></TR>
<TR>
<TD width="32%">NMI Unexpected Exceptions</TD>
<TD width="68%">A final check for unexpected exceptions before giving control to the Int 19 boot loader.  Failure is normally due to a memory parity error or an adapter failure</TD></TR>
<TR>
<TD width="32%">Boot Errors</TD>
<TD width="68%">Failure when the BIOS attempts to boot off the default drive set in CMOS is normally due to invalid CMOS drive setup or as given by an error message.  If the system hangs there is an error in the Master Boot Record or the Volume Boot Record</TD></TR></TBODY></TABLE>
<A href="http://bioscentral.com/postcodes/awardbios.htm#top">Source page & More</A></DIV>
AWARD Test Sequence after version 4.2

cvl · 發(fā)表于 2006-11-21 14:39:27

深層次，頂！Source page & More

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zwcd94w · 發(fā)表于 2006-11-21 19:39:45

就是看不懂但是還是謝謝啊

陶剛 · 發(fā)表于 2006-11-21 22:15:16

kankanle

yuxl2003 · 發(fā)表于 2006-11-21 22:28:03

有寫(xiě)看不懂
英語(yǔ)太差了。。。

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